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1 64mb: x16, x32 syncflash ?2002, micron technology, inc. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 advance ? ? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet microns production data sheet specifications. 64mb: x16, x32 syncflash memory syncflash ? memory features ? 125 mhz sdram-compatible read timing ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access ? programmable burst lengths: 1, 2 , 4, 8, or full page (read) 1, 2, 4, or 8 (write) ? lvttl-compatible inputs and outputs ? 3.0vC3.6v v cc , 1.65vC1.95v v cc q additional v hh hardware protect mode (rp#) ? supports cas latency of 1, 2, and 3 ? four-bank architecture supports true concurrent operation with zero latency read any bank while programming or erasing any other bank ? deep power-down mode: 50a (max) ? cross-compatible flash memory command set ? operating temperature range of -40 o c to +85 o c options marking ? configuration 4 meg x 16 (1 meg x 16 x 4 banks) 4m16 2 meg x 32 (512k x 32 x 4 banks) 2m32 ? read timing (cycle time) 10ns (100 mhz) @ cl2 -8 8ns (125 mhz) @ cl3 -8 10ns (100 mhz) @ cl3 -10 ? package 90-ball fbga fg part number example: mt28s4m16b1llfg-8 mt28s4m16b1ll C 1 meg x 16 x 4 banks MT28S2M32B1LL C 512k x 32 x 4 banks note: 1. the # symbol indicates signal is active low. key timing parameters access speed clock time setup hold grade frequency cl = 1* cl = 2* cl = 3* time time -8 125 mhz - - 7ns 2ns 1ns -10 100 mhz - - 7ns 2ns 1ns -8 100 mhz - 8ns - 2ns 1ns * cl = cas (read) latency pin assignment (top view) a b c d e f g h j k l m n p r 123 789 dnu dnu v ss q v ss q vccq v ss a4 a7 clk dqm1 vccq v ss v ss q dq11 dq13 dnu vccq dnu dnu dnu mcl a5 a8 cke rp# dq8 dq10 dq12 vccq dq15 v ss v ss q dnu dnu nc a3 a6 vccp a11 a9 vss dq9 dq14 v ss q vss dnu dnu vccq vccq vssq vcc a1 nc ras# dqm0 v ss q vccq vccq dq4 dq2 dnu v ss q dnu dnu dnu mcl a0 ba1 cs# we# dq7 dq5 dq3 v ss q dq0 vcc vccq dnu dnu nc a2 a10 nc ba0 cas# vcc dq6 dq1 vccq vcc 90-ball fbga C 2 meg x 32 a b c d e f g h j k l m n p r 123 789 dq26 dq28 v ss q v ss q vccq v ss a4 a7 clk dqm1 vccq v ss v ss q dq11 dq13 dq24 vccq dq27 dq29 dq31 dqm3 a5 a8 cke rp# dq8 dq10 dq12 vccq dq15 v ss v ss q dq25 dq30 nc a3 a6 vccp a9 dnu vss dq9 dq14 v ss q vss dq21 dq19 vccq vccq vssq vcc a1 nc ras# dqm0 v ss q vccq vccq dq4 dq2 dq23 v ss q dq20 dq18 dq16 dqm2 a0 ba1 cs# we# dq7 dq5 dq3 v ss q dq0 vcc vccq dq22 dq17 nc a2 a10 nc ba0 cas# vcc dq6 dq1 vccq vcc 90-ball fbga C 4 meg x 16
2 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance general description this 64mb syncflash ? data sheet is divided into two major sections. the sdram interface functional description details compatibility with the sdram memory, and the flash memory functional descrip- tion specifies the symmetrical-sectored flash architec- ture and functional commands. the 64mb syncflash devices are nonvolatile, elec- trically sector-erasable (flash), programmable read- only memory containing 67,108,864 bits. each of the x16s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. each of the x32s 16,777,216- bit banks is organized as 2,048 rows by 256 columns by 32 bits. the 64mb devices are organized into 16 indepen- dently erasable blocks. to ensure that critical firmware is protected from accidental erasure or overwrite, this device features sixteen (x32: 128k-dword; x16: 256k- word) hardware and software-lockable blocks. a four-bank architecture supports true concurrent operations. a read access to any bank can occur simul- taneously with a background program or erase op- eration to any other bank. syncflash memory has a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). read accesses to the memory are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. accesses begin with the registra- tion of an active command, followed by a read com- mand. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read command are used to select the starting column location for the burst access. the 64mb devices provide for programmable read burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. the x16 device features an 8-word internal write buffer and the x32 features an 8-dword internal write buffer that support mode regis- ter programmed burst write compatibility of 1, 2, 4, or 8 locations. syncflash memory uses an internal pipelined archi- tecture to achieve high-speed operation. the 64mb devices are designed to operate in 3.3v v cc and 1.8v v cc q, low-power memory systems. a deep power-down mode is provided, along with a power- saving standby mode. all inputs and outputs are lvttl-compatible. syncflash memory offers substantial advances in flash operating performance, including the ability to synchronously burst data at a high data rate with auto- matic column-address generation and the capability to randomly change column addresses on each clock cycle during a burst access. all flash operations are performed using either a hardware command sequence (hcs) or a software com- mand sequence (scs). the hcs operations are used by memory controllers with native syncflash support. standard sdram controllers can use scs operation to perform flash operations. please refer to microns web site ( www.micron.com/ syncflash ) for the latest data sheet.
3 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance table of contents functional block diagram C 4 meg x 16 ............... 4 C 2 meg x 32 ............... 5 pin and ball descriptions ....................................... 6 sdram interface functional description ....... 9 initialization ...................................................... 9 register definition ............................................. 9 mode register .............................................. 9 burst length ............................................ 9 burst type ............................................... 11 cas latency ............................................ 11 operating mode ..................................... 11 write burst mode ................................... 11 commands ........................................................ 12 truth table 1 (commands and dqm operation) ........ 12 truth table 2a (harware command sequences [hcs]) ................................................. 13 truth table 2b (software command sequences [scs]) .................................................. 14 command inhibit ........................................ 17 no operation (nop) ................................... 17 load mode register ..................................... 17 active ............................................................ 17 read ............................................................. 17 write ............................................................ 17 active terminate .......................................... 17 burst terminate ............................................ 17 load command register ............................. 17 operation .......................................................... 18 bank/row activation .................................. 18 reads ............................................................ 19 write bursts .................................................. 24 active terminate .......................................... 24 power-down ................................................ 24 clock suspend ............................................. 24 burst read/single write ............................... 25 truth table 3 (cke) .................................................. 26 truth table 4 (current state, same bank) .................. 27 truth table 5 (current state, different bank) ............. 28 flash memory functional description ............ 29 flash command sequence ............................... 29 hardware command sequence (hcs) ....... 29 software command sequence (scs) .......... 29 memory architecture ........................................ 30 protected blocks ........................................... 30 command execution logic (cel) ............... 30 internal state machine (ism) ...................... 30 ism status register ...................................... 30 output (read) operations .............................. 31 memory array ............................................. 32 status register .............................................. 32 device configuration registers ................... 32 input operations .............................................. 32 memory array ............................................. 32 command execution ........................................ 32 status register .............................................. 32 device configuration .................................. 33 program sequence ....................................... 33 erase sequence ............................................. 33 program and erase nvmode register ......... 34 block protect/unprotect sequence ................... 34 device protect sequence .............................. 34 chip initialize sequence .............................. 34 disable lcr sequence .................................. 35 reset/deep power-down mode ....................... 35 error handling .................................................. 35 program/erase cycle endurance ....................... 35 absolute maximum ratings ............................. 44 dc electrical characteristics and operating conditions .......................... 44 i cc specifications and conditions .................... 45 capacitance ....................................................... 45 electrical characteristics and recommended ac operating conditions (timing table) .. 46 ac functional characteristics .......................... 47 timing waveforms initialize and load mode register rp# .............................................................. 48 fcs .............................................................. 49 clock suspend mode ........................................ 50 reads read ............................................................. 51 alternating bank read accesses .................. 52 full-page burst ............................................. 53 dqm operation .......................................... 54 program/erase bank a followed by read to bank a .......... 55 bank a followed by read to bank b .......... 56
4 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance functional block diagram 4 meg x 16 ras# cas# clk cs# we# cke column- address counter/ latch 8 a0Ca11, ba0, ba1 dqm0C dqm1 12 address register 14 256 4,096 i/o gating dqm mask logic read data latch write drivers column decoder bank 0 memory array (4,096 x 256 x 16) bank 0 row- address latch & decoder high voltage switch/pump 4,096 sense amplifiers bank control logic dq0C dq15 16 16 16 12 bank 1 bank 2 bank 3 8 2 2 2 command execution logic mode register command decode state machine status reg. nvmode register 16 data input register data output register rp# v cc p id reg.
5 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance ras# cas# clk cs# we# cke column- address counter/ latch 8 a0Ca10, ba0, ba1 dqm0C dqm3 11 address register 13 256 8,192 i/o gating dqm mask logic read data latch write drivers column decoder bank 0 memory array (2,048 x 256 x 32) bank 0 row- address latch & decoder high voltage switch/pump 2,048 sense amplifiers bank control logic dq0C dq31 32 32 32 11 bank 1 bank 2 bank 3 8 2 4 4 command execution logic mode register command decode state machine status reg. nvmode register 16 data input register data output register rp# v cc p id reg. functional block diagram 2 meg x 32
6 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance (continued on next page) pin and ball descriptions tsop pin fbga ball numbers numbers symbol type description 68 j1 clk input clock: clk is driven by the system clock. all syncflash memory input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. 67 j2 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides standby opera- tion or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down modes, providing low standby power. cke may be tied high in systems where power-down modes (other than rp# deep power-down) are not required. 20 j8 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is consid- ered part of the command code. 19, 18, 17 j9, k7, k8 ras#, input command inputs: ras#, cas#, and we# (along with cs#) cas#, we# define the command being entered. 16, 71 k9, k1 x16: dqm0, input input/output mask: dqm is an input mask signal for write dqm1 accesses and an output enable signal for read accesses. input data is masked when dqm is sampled high during a write 16, 71, 28, k9, k1, f8, x32: dqm0 cycle. the output buffers are placed in a high-z state (after a 59 f2 Cdqm3 two-clock latency) when dqm is sampled high during a read cycle. for x16, dqm0 corresponds to dq0Cdq7, dqm1 corresponds to dq8Cdq15. for x32, dqm0 corresponds to dq0Cdq7, dqm1 corresponds to dq8Cdq15, dqm2 corre- sponds to dq16Cdq23, dqm3 corresonds to dq24Cdq31. dqm0Cdqm3 are in the same state when referenced as dqm. 25C27, g8, g9, f7, a0Ca11 input address inputs: a0Ca11 are sampled during the active 60C66, 24, f3, g1, g2, command (row address a0Ca11 [x16]; a0Ca10 [x32]) and 70 g3, h1, h2, read/write command (column-address a0Ca7) to select one j3, k3, g7 location in the respective bank. the address inputs provide the op-code during a load mode register command and the com-code during an lcr command. for x16: a11 is pin 66 (j3), and a9 is pin 70 (k3). 22, 23 j7, h8 ba0, ba1 input bank address input(s): ba0, ba1 define to which bank the active, read, or write command is being applied.
7 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance pin and ball descriptions (continued) tsop pin fbga ball numbers numbers symbol type description 30 k2 rp# input initialize/power-down: upon initial device power-up, a 100s delay after rp# has transitioned from low to high is required for internal device initialization, prior to issuing an executable command. rp# clears the status register, sets the internal state machine (ism) to the array read mode, and places the device in the deep power-down mode when low. all inputs, including cs#, are dont care and all outputs are high-z. when rp# = v hh , all protection modes are ignored during program and erase. this input also allows the device protect bit to be set to 1 (protected) and allows the block protect bits at locations 0 and 15 to be set to 0 (unprotected). rp# must be held high during all other modes of operation. 2, 4, 5, 7, r8, n7, r9, x16: dq0C i/o data i/o: data bus. 8, 10, 11, n8, p9, m8, dq15 13, 74, 76, m7, l8, l2, 77, 79, 80, m3, m2, p1, 82, 83, 85, n2, r1, n3, r2 2, 4, 5, 7, r8, n7, r9, x32: dq0C 8, 10, 11, n8, p9, m8, dq31 13, 74, 76, m7, l8, l2, 77, 79, 80, m3, m2, p1, 82, 83, 85, n2, r1, n3, 31, 33, 34, r2, e8, d7, 36, 37, 39, d8, b9, c8, 40, 42, 45, a9, c7, a8, 47, 48, 50, a2, c3, a1, 51, 53, 54, c2, b1, d2, 56 d3, e2 3, 9, 35, b2, b7, c9, v cc q supply dq power: 1.65vC1.95v; provide isolated power to dqs for 41, 49, d9, e1, l1, improved noise immunity. 55, 75, 81 m9, p2, p7, n9 6, 12, 32, b3, b8, c1, v ss q supply dq ground: provide isolated ground to dqs for improved 38, 46, 52, d1, e9, l9, noise immunity. 78, 84 m1, n1, p3, p8 1, 15, 29, a7, f9, l7, v cc supply power supply: 3.0vC3.6v. 43 r7 44, 58, 72, a3, f1, l3, v ss supply ground. 86 r3 (continued on next page)
8 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance pin and ball descriptions (continued) tsop pin fbga ball numbers numbers symbol type description 57 h3 v cc p supply program/erase supply voltage: v cc p must be tied externally to v cc . the v cc p pin sources current during device initialization, program, and erase operations. 14, 21, 69, e3, e7, h7, nc C no connect: these pins may be driven or left unconnected. 73 h9 31, 33, 34, e8, d7, d8, x16: dnu C do not use. 36, 37, 39, b9, c8, a9, 40, 42, 45, c7, a8, a2, 47, 48, 50, c3, a1, c2, 51, 53, 54, b1, d2, d3, 56 e2 70 k3 x32: dnu 28, 59 f8, f2 x16: mcl C must connect to vss.
9 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram sdram interface functional description in general, the 64mb syncflash memory devices (1 meg x 16 x 4 banks, 512k x 32 x 4 banks) are config- ured as a quad-bank, nonvolatile sdram that operate at 3.0vC3.6v and include a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x16s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. each of the x32s 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits. read accesses to the syncflash memory are identi- cal to sdr sdram operation. burst accesses start at a selected location and continue for a programmed num- ber of locations in a programmed sequence. accesses begin with the registration of an active command, followed by a read command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank; x32: a0Ca10, x16: a0Ca11 select the row). the address bits (a0Ca7) registered coincident with the read command are used to select the starting column location for the burst access. all non-read operations are controlled with either a hardware command sequence (hcs) or a software command sequence (scs). both the hcs and scs interface can be used to initiate any of the internal program, erase, initialization, or status operations. the term flash command sequence (fcs) refers to either hcs or scs operation. prior to normal operation, the syncflash memory must be initialized. the following sections provide detailed information covering device initialization, reg- ister definition, command descriptions, and device op- eration. initialization the device power-up procedure can be defined two ways. the first is a hardware initiated power-up, where power is applied to v cc , v cc q, and v cc p (simulta- neously). then, with the clock stable, rp# must be brought from low to high. after rp# transitions high, the power-up initialization process will complete within 100s. the second procedure is defined as a software initiated power-up. in this case the initialization is performed using the initialize device fcs opera- tion. when the initialize device command is used, the rp# pin does not require the low-to-high transi- tion typically required for initialization. after the ini- tialize device command has been issued, the power-up initialization process will complete within 100s. early completion of either initialization procedure can be detected by polling sr7 in the status register. after initialization, the syncflash device is in standby mode and ready for mode register programming or an executable command. after initial programming of the nvmode register, the contents are automatically loaded into the mode register during initialization and the device will power-up in the programmed state. note that when v cc is greater than 2.7v, either of the initialization procedures can be issued. register definition mode register the mode register is used to define the specific mode of operation of the syncflash memory. this definition includes the selection of a burst length, a burst type, a cas latency, and an operating mode, as shown in fig- ure 1. the mode register is programmed via the load mode register command and will retain the stored information until it is reprogrammed. the nvmode reg- ister settings are transferred into the mode register during initialization. the contents of the mode register may be copied into the nvmode register with a pro- gram nvmode register command. details on erase nvmode register and program nvmode register command sequences are found in the command ex- ecution section of the flash memory functional description. mode register bits m0Cm2 specify the burst length, m3 specifies the burst type (sequential or interleaved), m4Cm6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the syncflash memory are burst oriented, with the burst length being pro- grammable, as shown in figure 1. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. burst lengths of 1, 2, 4, or 8 locations are avail- able for both the sequential and the interleaved burst types (read or write), and a full-page burst is available for the sequential type (read only). the full-page burst can be used in conjunction with the burst termi- nate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result.
10 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram figure 1 mode register definition table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0Ca7 cn, cn+1, cn+2 page cn+3, cn+4... not supported 256 (location 0-255) cn-1, cn... note: 1. for a burst length of two, a1Ca7 select the block- of-two burst; a0 selects the starting column within the block. 2. for a burst length of four, a2Ca7 select the block- of-four burst; a0Ca1 select the starting column within the block. 3. for a burst length of eight, a3Ca7 select the block-of-eight burst; a0Ca2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0Ca7 select the starting column. 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0Ca7 select the unique column to be accessed, and mode register bit m3 is ignored. 7. burst write (x32: 1, 2, 4, or 8 dwords, x16: 1, 2, 4, or 8 words) is supported (not full page). 8. the contents of the mode register can be read using the read device configuration command (004h). m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved m6 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 10 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *program m11, m10 = 0, 0 to ensure compatibility with future devices. a11 11 1 when a read or write command is issued, a block of columns equal to the burst length is effectively se- lected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely se- lected by a1Ca7 when the burst length is set to two, by a2Ca7 when the burst length is set to four, and by a3C a7 when the burst length is set to eight. the remaining (least significant) address bit(s) are used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. note: 1. a11 and m11 are supported only by 4 meg x 16 configuration.
11 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram figure 2 cas latency clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop dont care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type, and the starting column address, as shown in table 1. cas latency the cas latency is the delay, in clock cycles, be- tween the registration of a read command and the availability of the first piece of output data. the la- tency can be set to one, two, or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 2. table 2 indicates the operating fre- quencies at which each cas latency setting can be used. reserved states should not be used, as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to read and write bursts (full-page burst write not supported). test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0Cm2 applies to both read and write bursts; however, if full-page burst length is selected in conjunction with m9 = 0, the burst write length is 8 words for the x16 and 8-dwords for the x32 (not full page). when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. table 2 cas latency allowable operating frequency (mhz) cas cas cas speed latency = 1 latency = 2 latency = 3 -8 50 mhz 100 mhz 125mhz -10 40 mhz 83 mhz 100 mhz
12 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram commands truth table 1 provides a quick reference of avail- able commands for sdram-compatible operation. this is followed by a written description of each command. additional truth tables appear later. truth table 1 sdram-compatible interface commands and dqm operation (notes: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) h xxxx x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 2 read (select bank, column and start read burst) l h l h x bank/col x 3 write (select bank, column and start write) l h l l x bank/col valid 3, 4 burst terminate l h h l x x active active terminate l l h l x x x 5 load command register l l l h x com-code x 6, 7 load mode register llllx op-code x 8 write enable/output enable CCCCl C active 9 write inhibit/output high-z CCCCh C high-z 9 note: 1. cke is high for all commands shown. 2. x32: a0Ca10, x16: a0Ca11 provide row address, and ba0 and ba1 determine which bank is made active. 3. a0Ca7 provide column address, and ba0 and ba1 determine which bank is being read from or written to. 4. a program setup command sequence (see truth table 2a) must be completed prior to executing a write. 5. active terminate is functionally equivalent to the sdram precharge command; however, precharge (deactivate row in bank or banks) is not required for syncflash memory. a10 low: ba0 and ba1 determine the bank to be active terminated. a10 high: all banks are active terminated and ba0 and ba1 are dont care. 6. a0Ca7 define the com-code, and a8Ca11 are dont care for this operation. see truth table 2a. 7. load command register (lcr) replaces the sdram auto refresh or self refresh mode, which is not required for syncflash memory. lcr is the first cycle for flash memory hardware command sequences (hcs). see truth table 2a. after the hardware lcr function is disabled, syncflash will treat sdram refresh or auto refresh commands as nops. a software command sequence (scs) is available to perform all operations described in truth table 2b. 8. a0Ca10 define the op-code written to the mode register. the mode register can be dynamically loaded each cycle, provided t mrd is satisfied. the default mode register value is stored in the nvmode register. the contents of the nvmode register are automatically loaded into the mode register during device initialization. 9. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay).
13 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram commands the following truth tables provide a quick reference of available commands for flash memory interface operation. a written descrip- tion of each command is found in the flash memory functional description section. truth table 2a C hardware command sequences (notes: 1C5; see notes on page 14.) first cycle second cycle third cycle bank bank bank operation cmd addr 6 addr dq rp# cmd 7 addr addr dq rp# cmd addr addr dq 8 rp# 9 notes read device configuration lcr 90h bank x h active ca row bank x h read ca col bank x h 11, 12 read status register lcr 70h x x h active x x x h read x x x h clear status register lcr 50h x x h erase setup/confirm lcr 20h bank x h active row bank x h write x bank d0h h/v hh 12, 13, 14 program setup/program lcr 40h bank x h active row bank x h write col bank d in h/v hh 12, 13, 14, 15 protect block/confirm lcr 60h bank x h active row 10 bank x h write x bank lbda( in )h/v hh 12, 13, 15, 16 protect device/confirm lcr 60h bank x h active x bank x h write x bank lbda( in )v hh 12, 13, 16 unprotect blocks/confirm lcr 60h bank x h active x bank x h write x bank lbdb( in )h/v hh 12, 13, 14, 15, 16 unprotect device/confirm lcr 60h bank x h active x bank x h write x bank lbdb( in )v hh 12, 13, 16 erase nvmode register lcr 30h bank x h active x bank x h write x bank c0h h 12, 13 program nvmode register lcr a0h bank l x h active x bank l x h write x bank l x h 12, 13, 17, 18 chip initialize lcr 68h bank x h active x bank x h write x bank c0h h 12, 13 disable hardware lcr lcr a0h bank u x h active x bank u x h write x bank u x h 12, 13, 17, 18, 19
14 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram truth table 2b C software command sequences (scs) (notes: 1, 2, 4, 5; see notes on page 16) (continued on next page) operation first second third fourth fifth sixth seventh eighth cycle cycle cycle cycle cycle cycle cycle cycle read device configuration 10 command active write active read addr = 88h 90h ca row ca col bank address = x x bank 12 bank 12 dq = xxxx rp# = h h h h read status register command active write active read addr = 88h 70h x x bank address = x x x x dq = x x x x rp# = h h h h clear status register command active write addr = 88h 50h bank address = x x dq = x x rp# = h h erase setup/confirm command active write active write active write active write addr = x 55h 55h 2ah 80h 20h row x bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55h x a0h x d0h rp# = h h h h h h h h/v hh program setup/confirm command active write active write active write active write addr = x 55h 55h 2ah 80h 40h row col bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55h x a0h x din rp# 9 = hhhhhhhh/v hh 15 protect block/confirm command active write active write active write active write addr = x 55h 55h 2ah 80h 60h row 11 x bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55 x a0h x lbda(in) 16 rp# 9 = hhhhhhhh/v hh 15 protect device confirm command active write active write active write active write addr = x 55h 55h 2ah 80h 60h x 10 x bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55h x a0h x lbda(in) 16 rp# 9 = hhhhhhhv hh
15 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram truth table 2b C software command sequences (scs) (continued) (notes: 1, 2, 4, 5; see notes on page 16) operation first second third fourth fifth sixth seventh eighth cycle cycle cycle cycle cycle cycle cycle cycle unprotect block/confirm 10, 16 command active write active write active write active write addr = x 55h 55h 2ah 80h 60h x 11 x bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55h x a0h x lbdb(in) 16 rp# 5 = hhhhhhhv hh unprotect device/confirm command active write active write active write active write addr = x 55h 55h 2ah 80h 60h x x bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55h x a0h x lbdb(in) 16 rp# 5 = hhhhhhhh/v hh erase nvmode register command active write active write active write active write addr = x 55h 55h 2ah 80h 30h x x bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55h x a0h x c0h rp# = h h h h h h h h program nvmode register 18 command active write active write active write active write addr = x 55h 55h 2ah 80h a0h x x bank address = x bank l 12 bank l 12 bank l 12 bank l 12 bank l 12 bank l 12 bank l 12 dq = x x x 55h x a0h x x rp# = h h h h h h h h disable hardware lcr 19 command active write active write active write active write addr = x 55 55h 2ah 80h a0h x x bank address = x bank u 12 bank u 12 bank u 12 bank u 12 bank u 12,18 bank u 12,18 bank u 12,18 dq = x x x 55h x a0h x x rp# = h h h h h h h h chip initialize command active write active write active write active write addr = x 55h 55h 2ah 80h 68h x x bank address = x bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 bank 12 dq = x x x 55h x a0h x c0h rp# = h h h h h h h h
16 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram note: 1. cmd = command: decoded from cs#, ras#, cas#, and we# inputs. 2. nop/command inhibit/burst terminate/active terminate commands may be issued throughout the hcs or scs. addtitionally, load command register may be issued throughout the scs. 3. after a program or erase operation is registered to the ism and prior to completion of the ism operation, a read to any location in the bank under ism control will output the contents of the row activated prior to the lcr/active/write sequence (see note 14). 4. to meet the t rcd specification, the appropriate number of nop/command inhibit commands must be issued between active and read/write commands. 5. the erase, program, protect, and unprotect operations are self-timed. the status register may be polled to monitor these operations. 6. x32: a8Ca10, x16: a8Ca11 are dont care. 7. a row will not be opened when active is preceded by lcr. active is considered a nop. 8. x32 data inputs, dq8Cdq31 are dont care except for d in , where all dq31Cdq0 are driven. x16 data inputs, dq8Cdq15 are "dont care" except for d in , where all dq15Cdq0 are driven. data outputs: all unused bits are driven low. 9. v hh = 7.0vC8.5v 10. address must be any row address in the block desired to be protected. 11. ca row , ca col = configuration address this value changes depending on the bit location being accessed ca row = x02h for block protect bit, which corresponds to the block row address: x32: x = 0, 2, 4, or 6h x16: x = 0, 4, 8, or ch for all other bits ca row = xxxh (dont care) ca col = values shown below 00h = manufacturer compatibility id = 2ch 01h = device id mt28s4m16b1 = d5h device id mt28s2m32b1 = d4h 02h = block protect bit (bpb) 03h = device protect bit (dpb) 04h = mode register 05h = hardware load command register (lcr) bit 06h/07h = reserved for future use 12. ba = bank address must match for all the cycles, except for manufacturer id/device id/device protect where it is xxh. 13. the proper command sequence (lcr/active/write) is needed to initiate an erase, program, protect, or unprotect operation. 14. if the device protect bit is not set, rp# = v ih unprotects all sixteen ( x32: 128k-dword, x16: 256k-word ) erasable blocks, except for blocks 0 and 15. when rp# = v hh , all sixteen ( x32: 128k-dword, x16: 256k-word) erasable blocks (including blocks 0 and 15) will be unprotected, and the device protect bit will be ignored. if the device protect bit is set and rp# = v ih , the block protect bits cannot be modified. 15. if the device protect bit is set, then an erase, program, protect, or unprotect operation can still be initiated by bringing rp# to v hh prior to the write command cycle and holding it at v hh until the operation is completed. 16. lbda = lock bit data 01h = set block protect bit f1h = set device protect bit if the dpb is not set, rp# = v ih ; all blocks can be set if the dpb is set, rp# = v ih ; bpbs cannot be modified rp# = v hh ; all bpbs can be modified to set dpb, rp# = v hh is a must rp# = v hh ; all blocks including 0 and 15 are unprotected (reset); dpb does not matter lbdb = lock bit data d0h = clear block and device protect bit if the dpb is not set, rp# = v ih ; all blocks except 0 and 15 are unprotected (reset) if the dpb is set, rp# = v ih ; block protect bits cannot be modified rp# = v hh ; all blocks including 0, 15, and dpb are unprotected (reset) 17. bank l: [ba1,ba0] = [0,0] or [0,1] bank u: [ba1 ba0] = [1,0] or [1,1] 18. if [ba1, ba0] = [0,0] or [0,1], then write nvmode register operation is performed. if [ba1, ba0] = [1,0] or [1,1], then disable hardware lcr operation is performed. 19. hardware lcr is preset to 1. hardware lcr bit is a one time programmable bit and cannot be reset to 1 after programmed to 0.
17 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram command inhibit the command inhibit function prevents new commands from being executed by the syncflash memory, regardless of whether the clk signal is en- abled. the syncflash memory is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to a syncflash memory that is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0Ca10. see the mode register heading in the register definition section. the load mode register command can only be issued when all banks are idle, and a subse- quent executable command cannot be issued until t mrd is met. the data in the nvmode register is auto- matically loaded into the mode register upon power- up initialization and is the default mode setting unless dynamically changed with the load mode regis- ter command. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs (x32: a0Ca10, x16: a0Ca11) selects the row. this row remains active for accesses until the next active command, power-down or reset. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0Ca7 selects the starting column location. read data appears on the dqs subject to the logic level on the dqm input two clocks earlier. if a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was regis- tered low, the dqs will provide valid data. write the write command is used to initiate a burst write access. a write command must be preceded by lcr/ active. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0Ca7 se- lects the column location. input data appearing on the dqs is written to the memory array, subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that word/column location. a write command with dqm high is con- sidered a nop. active terminate active terminate, which replaces the sdram precharge command, is not required for syncflash memory, but is functionally equivalent to the sdram precharge command. active terminate can be issued to terminate a burst read in progress and may or may not be bank specific. burst terminate the burst terminate command is used to trun- cate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated as shown in the operation section of this data sheet. burst terminate is not bank specific. load command register (hcs only) the load command register command in the hcs is used to initiate flash memory control commands to the command execution logic (cel). the cel re- ceives and interprets commands to the device. these commands control the operation of the internal state machine and the read path (i.e., memory array, id reg- ister or status register). however, there are restrictions on what commands are allowed in this condition. see the command execution section of flash memory func- tional description for more details.
18 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram figure 3 activating a specific row in a specific bank operation bank/row activation before any read or write commands can be is- sued to a bank within the syncflash memory, a row in that bank must be opened. (note: a row will not be activated for lcr/active/read or lcr/active/write com- mand sequences. see flash memory architecture sec- tion for additional information). this is accomplished via the active command, which selects both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specifi- cation of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks rounded to 3. this is reflected in figure 4, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specifi- cation limits from time units to clock cycles). a subsequent active command to a different row in the same bank can be issued without having t o close a previous active row, provided the minimum time in- terval between successive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. cs# we# cas# ras# cke clk a0Ca10 row address high ba0,ba1 bank address a0Ca11 x32: x16: clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd dont care figure 4 example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3
19 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram reads read bursts are initiated with a read command, as shown in figure 5. the starting column and bank addresses are pro- vided with the read command. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the read command. each sub- sequent data-out element will be valid by the next positive clock edge. figure 6 shows general timing for one, two and three cas latency settings. upon completion of a burst, assuming no other com- mands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data from any read burst may be truncated with a subsequent read command, and data from a fixed- length read burst may be immediately followed by data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst that is being truncated. figure 5 read command figure 6 cas latency the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 7 for cas latencies of one, two and three; data element n + 3 is either the last of a burst of four, or the last desired of a longer burst. the syncflash memory uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initi- ated on any clock cycle following a previous read com- mand. full-speed, random read accesses within a page can be performed as shown in figure 8, or each subse- quent read may be performed to a different bank. cs# we# cas# ras# cke clk column address a0Ca7 ba0, ba1 bank address high clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop dont care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
20 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram figure 7 consecutive read bursts clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n dont care nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles note: each read command may be to either bank. dqm is low. cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3
21 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram figure 8 random read accesses within a page clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n dont care d out n d out a d out x d out m read note: each read command may be to either bank. dqm is low. read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cas latency = 1 cas latency = 2 cas latency = 3
22 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram figure 9 hcs read to write data from any read burst may be truncated with a subsequent write command and data from a fixed- length read burst may be immediately followed by data from a subsequent write command (subject to bus turnaround limitations). the write may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be the possibility that the device driving the input data would go low-z before the syncflash memory dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention as shown in figure 9. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to sup- press data-out from the read. once the write com- mand is registered, the dqs will go high-z (or remain high-z) regardless of the state of the dqm signal. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buff- ers) to ensure that the written data is not masked. fig- ure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle. a fixed-length or full-page read burst can be trun- cated with active terminate (which may or may not be bank specific) or burst terminate (which is not bank specific). the active terminate or burst terminate command should be issued x cycles be- fore the clock edge at which the last desired data ele- ment is valid, where x equals the cas latency minus one. this is shown in figure 11 for each possible cas latency; data element n + 3 is the last desired data element of a burst of four or the last desired of a longer burst. read lcr active write nop clk t2 t1 t4 t3 t0 dqm, h dq d out n command d in b address bank, col n bank, col b ds t hz t t ck note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. if a cas latency of one is used, then dqm is not required. 40h bank row figure 10 hcs read to write with extra clock cycle dont care read lcr nop active nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 t ds t hz note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. bank, row 40h
23 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram figure 11 terminating a read burst clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 dont care note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles
24 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram write bursts write bursts are initiated with a write command as shown in figure 12. write commands are preceded by an fcs program command. the 2 meg x 32 features a 32-byte internal buffer, while the 4 meg x 16 features a 16-byte internal write buffer which supports mode reg- ister programmed burst writes of 1, 2, 4, or 8 locations. the starting column and bank addresses are provided with the write command. once a write command is registered, a read command can be executed as de- fined by truth tables 4 and 5. an example is shown in figure 14. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored (see figure 13). active terminate the active terminate command is functionally equivalent to the sdram precharge command. un- like sdram, syncflash memory does not require a precharge command to deactivate the open row in a particular bank or the open rows in all banks. asserting input a10 high during an active terminate com- mand will terminate a burst read in any bank. when a10 is low during an active terminate command, ba0 and ba1 will determine which bank will undergo a terminate operation. active terminate is consid- ered a nop for banks not addresssed by a10, ba0, ba1 (see figure 15). power-down power-down occurs if cke is registered low coinci- dent with a nop or command inhibit when no ac- cesses are in progress. entering power-down deacti- vates the input and output buffers (excluding cke) after internal state machine operations (including write operations) are completed for power savings while in standby (see figure 16). the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see the reset/deep power-down description in the flash memory functional description for maximum power savings mode. clock suspend the clock suspend mode occurs when a column ac- cess/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, freezing the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the in- put pins at the time of a suspended internal clock edge is ignored, any data present on the dq pins remains driven, and burst counters are not incremented, as long as the clock is suspended (see examples in figures 17 and 18). figure 12 write command cs# we# cas# ras# cke clk column address a0Ca7 ba0, ba1 bank address high ck dq d in n t2 t1 t3 t0 command address nop nop dont care write d in n + 1 nop bank, col n note: burst length = 2. dqm is low. figure 13 write burst
25 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram ck dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) note: dqms are low, and burst length >1. burst terminate command causes data on dq to become invalid. figure 14 hcs write to read clk dq t2 t1 t3 t0 command address write bank, col n d in n read nop bank, col b nop note: a cas latency of two is used for illustration. the write command may be to any bank and the read command may be to any bank. dqm is low. for more details, refer to truth tables 4 and 5. db out figure 15 terminating a write burst dq command address write bank, col n d in n nop nop ck t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 note: for this example, burst length = 4 or greater, and dqm is low. figure 17 clock suspend during write burst t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) coming out of a power-down sequence (active), t cks (cke setup time) must be greater than or equal to 3ns. figure 16 power-down figure 18 clock suspend during read burst dont care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 note: for this example, cas latency = 2, burst length = 4 or greater, and dqm is low. cke internal clock nop clock suspend mode is exited by registering cke high; the internal clock and related operation will re- sume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by pro- gramming the write burst mode bit (m9) in the mode register to a logic 1. all write commands result in the access of a single column location (burst of one). read commands access columns according to the pro- grammed burst length and sequence.
26 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram truth table 3 C cke (notes: 1C4) cke n-1 cke n current state command n action n notes l l clock standby x maintain clock standby clock suspend x maintain clock suspend l h clock standby command inhibit or nop exit clock standby 5 clock suspend x exit clock suspend 6 h l no burst in progress command inhibit or nop clock standby reading valid clock suspend h h see truth table 4 note: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the syncflash memory immediately prior to clock edge n . 3. command n is the command registered at clock edge n and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the idle state in time for clock edge n + 1 (provided that t cks is met). 6. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1 .
27 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram truth table 4 C current state bank n ; command to bank n (notes: 1C6) current state cs# ras#cas# we# command/action notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) l l h h active (select and activate row) idle l l l h load command register llll load mode register 7 l l h l active terminate 8 l h l h read (select column and start read burst) row active l h l l write (select column and start write) l l h l active terminate 8 l l l h load command register l h l h read (select column and start new read burst) read l l h l active terminate 8 l h h l burst terminate 9 l l l h load command register write l h l h read (select column and start new read burst) 10 l l l h load command register note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 3). 2. this table is bank specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank, when in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank is not in read or write mode. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated and has not yet terminated or been terminated. write: a write operation has been initiated to the syncflash internal state machine (ism) and has not yet completed. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank, should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table 4, and according to truth table 5. active terminate: starts with registration of an active terminate command and ends on the next clock cycle. the bank will then be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the syncflash memory will be in the all banks idle state. initialize mode: starts with rp# transitioning from low to high and ends after 100s delay. 6. all states and sequences not shown are illegal or reserved. 7. not bank specific; requires that all banks are idle. 8. may or may not be bank specific. 9. not bank specific; burst terminate affects the most recent read burst, regardless of bank. 10. a read operation to the bank under ism control will output the contents of the row activated prior to the lcr/active/ write sequence (see truth table 2a).
28 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory sdram truth table 5 C current state bank n ; command to bank m (notes: 1C6) current state cs# ras#cas# we# command/action any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row l l h h active (select and activate row) activating, l h l h read (select column and start read burst) active, or l h l l write (select column and start write) active l l h l active terminate terminate l l l h load command register l l h h active (select and activate row) read l h l h read (select column and start new read burst) l l h l active terminate l l l h load command register l l h h active (select and activate row) l h l h read (select column and start read burst) write l l h l active terminate l h h l burst terminate l l l h load command register (hcs) note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 3). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank is not in initialize, read, write mode. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated and has not yet terminated or been terminated. write: a write operation has been initiated to the syncflash ism and has not yet completed. 4. load mode register command may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved.
29 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash flash memory functional description the syncflash memory incorporates a number of features that make it ideally suited for code storage and execute-in-place applications on an sdram bus. the memory array is segmented into individual erase blocks. each block may be erased without affecting data stored in other blocks. these memory blocks are read, programmed, and erased by issuing commands to the command execution logic (cel). the cel con- trols the operation of the internal state machine (ism), which completely controls all read device configu- ration, read status register, clear status register, reset device/confirm, program setup/confirm, protect blocks/confirm, protect device/confirm, unprotect device /confirm, unprotect blocks/confirm, erase nvmode register, program nvmode register, disable hardware lcr, erase setup confirm and chip initialization operations. the ism pro- tects each memory location from overerasure and opti- mizes each memory location for maximum data reten- tion. in addition, the ism greatly simplifies the control necessary for programming the device in-system or in an external programmer. the flash memory functional description provides detailed information on the operation of the syncflash memory and is organized into these sections: ? command interface ? memory architecture ? output (read) operations ? input operations ? command execution ? reset/power-down mode ? error handling ? program/erase cycle endurance flash command sequence all flash operations are performed using either a hardware command sequence (hcs) or a software com- mand sequence (scs). the hcs operations are used in systems that support the load command regis- ter (lcr) command. in systems that do not have the ability to generate an lcr command, scs operations can be used for flash operations. a flash command sequence (fcs) is used to describe flash operations where the actual implementation (hcs or scs) is not relevant. hardware command sequence (hcs) all hcs operations are executed with lcr, lcr/ active/read, or lcr/active/write commands and command sequences as defined in truth tables 1 and 2a. see program/erase diagram for timing in- formation. see the sdram interface functional de- scription for information on reading the memory array. address pins a0Ca7 are used to input 8-bit com- mands during the lcr command cycle. this command will identify which flash operation is initiated. certain lcr/active/write command sequences re- quire an 8-bit confirmation code on the write cycle. the confirmation code is input on dq0Cdq7. software command sequence (scs) flash operations can also be performed using an scs. the scs uses a series of standard cpu read and write op-codes to perform flash operations. this com- mand interface is similar to the multistep sequence common in standard flash components. table 3 is an example of programming data into a particular address using scs. see truth table 2b for a description of scs operations. table 3 1 software code to program data value 1234h to address 0000h using scs assembly code executed sdram commands issued op-code address, data command bank address data write 00000055h, 00000000h active 0h 000h xxxx write 0h 55h 0000h write 0000552ah, 00000055h active 0h 055h xxxx write 0h 2ah 0055h write 00008040h, 000000a0h active 0h 080h xxxx write 0h 40h 00a0h write 00000000h, 00001234h active 0h 000h xxxx write 0h 00h 1234h note: 1. this is a programming example for the 4 meg x 16 .
30 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash when a cpu executes a write op-code to a memory address configured for sdram, the memory controller issues an active command followed by a write com- mand. a similar active/read pair is also issued dur- ing a read operation. by issuing active/write and active/read pairs with predefined address and data values, any of the flash commands can be performed. memory architecture the 64mb syncflash memory is a four-bank archi- tecture with four erasable blocks per bank. by erasing blocks rather than the entire array, the total device endurance is enhanced, as is system flexibility. only the erase and block protect functions are block ori-ented. the four banks have simultaneous read- while-write functionality. an ism program or erase operation to any bank can occur simultaneously to a read to any other bank. the syncflash memory has a single background operation ism to control power-up initialization, erase, program, and protect operations. ism op- erations are initiated with an hcs or scs. only one ism operation can occur at any time; however, certain other commands, including read operations, can be per- formed while an ism operation is taking place. a new hcs or scs will not be permitted until the current ism operation is complete. an operational command controlled by the ism is defined as either a bank-level operation or a device- level operation. program and erase are bank-level ism operations. after an ism bank-level operation has been initiated, a read may be issued to any bank; however, a read to the bank under ism control will output the contents of the row activated prior to the hcs or scs. chip initialize, hardware lcr dis- able, erase nvmode register, program nvmode register, block protect, device pro- tect, and unprotect all blocks are device-level ism operations. once an ism device-level operation has been initiated, a read to any bank will output the contents of the array. a read status register com- mand sequence may be issued to determine comple- tion of the ism operation. when sr7 = 1, the ism opera- tion is complete and a new ism operation may be initi- ated. protected blocks the 64mb syncflash devices are organized into 16 erasable memory blocks. each block may be software protected by issuing the appropriate fcs for a block protect operation. the blocks at locations 0 and 15 have additional protection to prevent inadvertent program or erase operations in platforms where vih is not available. once a protect block operation has been executed to these blocks, an unprotect all blocks operation will unlock all blocks except the blocks at locations 0 and 15 unless rp# = v hh . this provides additional secu- rity for critical code during in-system firmware updates should an unintentional power disruption or system reset occur. a second level of block protection is possible by completing a hardware device protect opera- tion. device protect prevents block protect bit modification. the protection status of any block may be checked by reading the protect bits with a read device configu- ration command sequence. command execution logic (cel) syncflash operations are executed by issuing the appropriate commands to the cel. the cel receives and interprets commands to the device. these com- mands control the operation of the ism and the read path (i.e., memory array, device configuration, or sta- tus register). commands may be issued to the cel while the ism is active. however, there are restrictions on what commands are allowed in this condition. see the command execution section for more details. internal state machine (ism) power-up initialization, erase, program, and pro- tect timings are simplified by using an ism to control all programming algorithms in the memory array. the ism ensures protection against overerasure and optimizes programming margin to each cell. during program operations, the ism automati- cally increments and monitors program attempts, verifies programming margin on each memory cell and updates the ism status register. when block erase is performed, the ism automatically overwrites the en- tire addressed block (eliminates overerasure), incre- ments and monitors erase attempts, and sets bits in the ism status register. ism status register the 16-bit ism status register allows an external processor to monitor the status of the ism during de- vice initialization, erase nvmode register, pro- gram nvmode register, program, erase, block protect, device protect or unprotect all blocks, and any related errors. ism operations and related errors can be monitored by reading status register bits on dq0Cdq8. all of the defined bits are set by the ism, but only the ism status bits (sr0, sr1, sr2, sr7) are cleared by the ism. the erase/unprotect block, program/protect block, and device protection bits must be cleared by
31 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash the host system using the clear status register command. this allows the user to choose when to poll and clear the status register. for example, the host system may perform multiple program operations before checking the status register instead of checking after each individual program. a v cc power sequence error is cleared by re- initializing the device. asserting the rp# signal or powering down the de- vice will also clear the status register. output (read) operations syncflash memory features three different types of reads. depending on the mode, a read operation will produce data from the memory array, status regis- ter, or one of the device configuration registers. syncflash memory is in the array read mode unless a status register or device register read is initiated or in progress. a read to the device configuration register or the status register must be issued as defined by the fcs. the burst length of data-out is defined by the mode register settings. reading the device configuration reg- ister or status register will not disrupt data in a previ- ously open (or activated) page. when the burst is complete, a subsequent read will read the array. how- ever, several differences exist and are described in the following section. moving between modes to perform a specific read will be covered in the command execu- tion section. figure 20 4 meg x 16 memory address map 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block 256k-word block bank 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h fff c00 bff 800 7ff 400 3ff 000 fff c00 bff 800 7ff 400 3ff 000 fff c00 bff 800 7ff 400 3ff 000 fff c00 bff 800 7ff 400 3ff 000 bank 1 bank 2 bank 3 unlock blocks (rp# = v hh ) word-wide (x16) unlock blocks (rp# = v ih ) bank column row address range note: see block lock and unlock flowchart sequences for additional information. 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block 128k-dword block bank 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h 7ff 600 5ff 400 3ff 200 1ff 000 7ff 600 5ff 400 3ff 200 1ff 000 7ff 600 5ff 400 3ff 200 1ff 000 7ff 600 5ff 400 3ff 200 1ff 000 bank 1 bank 2 bank 3 unlock blocks (rp# = v hh ) dword-wide (x32) unlock blocks (rp# = v ih ) bank column row address range figure 19 2 meg x 32 memory address map
32 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash memory array a read command to any bank will output the con- tents of the memory array. while a program or erase ism operation is in progress, a read to any location in the bank under ism control will output the contents of the row activated prior to an fcs; a read to any other bank will output the contents of the array. all com- mands and their operations are covered in the sdram interface functional description section. status register reading the status register requires an fcs. the status register contents are latched on the next posi- tive clock edge subject to cas latencies. the burst length of the status register data-out is defined by the mode register. all commands and their operations are covered in the command execution section. device configuration registers to read the device id, manufacturer compatibility id, device protection status, block protect status, and the hardware lcr disable bit, the appropriate com- mand sequence for read device configuration must be issued. this is the same input sequencing used when reading the status register, except that spe- cific addresses must be issued. input operations an fcs is required to program the array, or to per- form an erase, protect, unprotect, or hard- ware lcr disable operation. the first cycle of an input operation is an fcs operation where inputs a0C a7 determine the input command being executed to the cel. an input operation will not disrupt data in a previously opened page. the dq pins are used either to input data to the array or to input a command to the cel during the write cycle. more information describing how to program, erase, protect, or unprotect the device is provided in the com- mand execution section. memory array programming or erasing the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. setting any bit to a logic 1 re- quires that the entire block be erased. programming a protected block requires that the rp# pin be brought to v hh . a0Ca10 (x32), a0Ca11 (x16) provide the address to be programmed, while the data to be programmed in the array is input on the dq pins. the data and ad- dresses are latched on the rising edge of the clock. details on how to input data to the array is covered in the command execution section. command execution commands are issued to bring the device into dif- ferent operational modes. each mode has specific op- erations that can be performed while in that mode. all hcs modes require that an lcr/active/read or lcr/ active/write sequence be issued, except clear sta- tus register, which is a single lcr command. in- puts a0Ca7 during the fcs determine the operation being performed. the following section describes the properties of each mode, and truth tables 1, 2a, and 2b list all commands and command sequences re- quired to perform the desired operation. read-while- write functionality allows a background operation pro- gram or erase to any bank while simultanously reading any other bank. the hcs operations in truth table 2a must be com- pleted on consecutive clock cycles. however, in order to reduce bus contention issues, an unlimited number of nops or command inhibits can be issued throughout the lcr/active/write command sequence. for additional protection, these command sequences must have the same bank address for the three com- mand cycles. the scs operations described in truth table 2b must also be completed on adjacent clock cycles. the scs operation will allow nop, command inhibit, refresh, and burst terminate commands to be issued during the sequence without aborting the se- quence. all steps in the scs must access the same bank or the operation will be aborted and the device will return to the read array mode. if the bank address changes during the fcs or if the command sequences are not consecutive (other than nops and command inhibits), the program and erase status bits (sr4 and sr5) will be set and the de- sired operation will be aborted. for additional protection, these command se- quences must have the same bank address during all command cycles. status register reading and clearing the status register requires an fcs. during status reads, the status register contents are latched on the next positive clock edge, subject to cas latencies, for a burst length defined by the mode register.
33 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash device configuration to read the device id, manufacturer compatibility id, device protect bit, and each of the block protect bits, the appropriate fcs operation for read device configuration must be issued. specific configura- tion addresses must be issued to read the desired in- formation. the manufacturer compatibility id is read at 000h; the device id is read at 001h. the manufac- turer compatibility id and device id are output on dq0Cdq7. the device protect bit is read at 003h; and each of the block protect bits is read on the third ad- dress location within each block (x02h). the device and block protect bits are output on dq0. the mode regis- ter is read from address 004h. the hardware load com- mand register bit is available on bit 0 of address 005h. a low on bit zero means that hcs operations are disabled and a high means that hcs operations are allowed. the device configuration register contents are out- put subject to cas latencies for a burst length defined by the mode register. program sequence using an hcs operation, three commands on con- secutive clock edges are required to input data to the array (nops and command inhibits are permitted between cycles). see table 2a. in the first cycle, load command register is issued with program setup (40h) on a0Ca7, and the bank address is issued on ba0, ba1. the next command is active, which identifies the row address and confirms the bank address. the third cycle is write, during which the column address, the bank address, and data are issued. to perform a program operation using an scs op- eration, the system executes a series of write op-codes using a predetermined set of address/data values (see truth table 2b). the scs operation will result in the command register being loaded with the program command (40h), and the cel being loaded with the address and data value to be programmed. the ism status bit will be set on the following clock edge (subject to cas latencies). while the ism is programming the array, the ism status bit (sr7) will be at 0. when the ism status bit (sr7) is set to a logic 1, programming is complete, and the bank will be in the array read mode and ready for a new ism operation. programming hardware-protected blocks requires that the rp# pin be set to v hh during the fcs, and rp# must be held at v hh until the ism program operation is complete. the program and erase status bits (sr4 and sr5) will be set and the operation aborted if the fcs command sequence is not completed on consecu- tive cycles or the bank address changes for any of the three cycles. after the ism has initiated programming, it cannot be aborted except by a reset or by powering down the device. doing either while programming the array will corrupt the data being written. erase sequence executing an erase sequence will set all bits within a block to logic 1. the hcs necessary to execute an erase is similar to that of a program. to provide added security against accidental block erasure, three con- secutive command sequences on consecutive clock edges are required to initiate an erase of a block. see table 2a. in the first cycle, load command regis- ter is issued with erase setup (20h) on a0Ca7, and the bank address of the block to be erased is issued on ba0, ba1. the next command is active, where a10, a11, ba0, and ba1 provide the address of the block to be erased. the third cycle is write, during which erase confrim (d0h) is issued on dq0Cdq7 and the bank address is reissued. the ism status bit will be set on the following clock edge (subject to cas latencies). after erase confirm (d0h) is issued, the ism will start erasing the addressed block. when the erase operation is complete, the bank will be in the array read mode and ready for an executable command. erasing hardware-protected blocks also requires that the rp# pin be set to v hh prior to the third cycle (write), and rp# must be held at v hh until the erase operation is complete (sr7 = 1). if the hcs is not completed on consecutive cycles (nop, command inhibit, precharge, and refresh are permitted between cycles) or the bank address changes for one or more of the command cycles, the program and erase status bits (sr4 and sr5) will be set. during the scs operation, eight commands on con- secutive clock edges are required to input data to the array (nop and command inhibit are permitted between cycles). see table 2b. after the first five setup cycles, the next three cycles are identical to the normal lcr command sequence except the command for the first of last three cycles is a write instead of an lcr. the ism status bit is set on the following clock edge (subject to cas latencies), indicating the erase op- eration is in progress. program and erase nvmode register the contents of the mode register may be copied into the nvmode register with a program nvmode register command. prior to programming the nvmode register, an erase nvmode register command sequence must be completed to set all bits in the nvmode register to logic 1. the command sequence necessary to execute an erase nvmode register and program nvmode register is similar to that
34 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash of a program sequence. see truth tables 2a and 2b for more information on the fcs operations necessary to complete erase nvmode register and program nvmode register. block protect/unprotect sequence executing a block protect sequence enables the first level of software/hardware protection for a given block. the command sequence necessary to execute a block protect is similar to that of a program sequence. to provide added security against accidental block pro- tection, three consecutive command cycles are re- quired to initiate a block protect during a normal hcs. in the first cycle, load command register is issued with protect setup (60h) on a0Ca7, and the bank address of the block to be protected is issued on ba0, ba1. the next cycle is active, which identifies a row in the block to be protected and confirms the bank address. the third cycle is write, during which block protect confirm (01h) is issued on dq0Cdq7, and the bank address is reissued. the ism status bit is set on the following clock edge (subject to cas latencies), indicating the protect operation is in progress. if the lcr/active/write is not completed on con- secutive cycles (nop and command inhibit, re- fresh, and precharge are permitted between cycles), or the bank address changes, the write and erase status bits (sr4 and sr5) will be set and the op- eration will be aborted. when the ism status bit (sr7) is set to a logic 1, the protect is complete. during the scs operation, eight commands on con- secutive clock edges are required to input data to the array (nop, command inhibit, refresh, and precharge are permitted between cycles). after the first six setup cycles, the last 2 cycles are identical to the normal hcs. the ism status bit is set on the following clock edge (subject to cas latencies) indicating the protect operation is in progress. once a block protect bit has been set to a 1 (pro- tected), it can only be reset to a 0 if the unprotect all blocks command is executed. the unprotect all blocks command sequence is similar to the block pro- tect sequence; however, in the last fcs cycle, a write is issued with unprotect all blocks confirm (d0h) and addresses are dont care. for additional information, refer to truth tables 2a and 2b. the blocks at locations 0 and 15 have additional security. once the block-protect bits at locations 0 and 15 have been set to a 1 (protected), each bit can only be reset to a 0 if rp# is brought to v hh prior to the third cycle (write) of the unprotect operation and held at v hh until the operation is complete (sr7 = 1). if the device protect bit is set, rp# must be brought to v hh prior to the last fcs cycle and held at v hh until the block protect or unprotect all blocks op- eration is complete. to check a blocks protect status, a read device con- figuration command sequence may be issued. device protect sequence executing a device protect command sequence sets the device protect bit to a 1 and prevents block pro- tect bit modification. the command sequence neces- sary to execute a device protect is similar to that of a program sequence. during normal hcs operation, load command register is issued in the first cycle with protect setup (60h) on a0Ca7, and a bank address is issued on ba0, ba1. the bank address is dont care, but the same bank address must be used for all three cycles. the next cycle is active. the third cycle is write, during which device protect (f1h) is is- sued on dq0Cdq7. rp# must be brought to v hh prior to registration of the write command. during the scs, eight commands on consecutive clock edges are required to input data to the array (nop, command inhibit, refresh, precharge, and burst terminate are permitted between cycles). after the first five setup cycles, the last three cycles are indentical to the normal hcs, except the command for the first of the last three cycles is a write instead of an lcr. the ism status bit is set on the following clock edge (subject to cas latencies). rp# must be held at v hh until the protect operation is complete (sr7 = 1). once the device protect bit is set, it can be reset by issuing an unprotect block command with rp# = v hh . with the device protect bit set to a 1, block protect or block unprotect is prevented unless rp# is at v hh during either operation. the device pro- tect bit does not affect program or erase operations. chip initialize sequence executing a chip initialize sequence can be accom- plished one of two ways. the first option is a hardware initiated power-up using the rp# transition to initiate a reset. a successful entry into the reset mode requires that rp# be held low for a minimum of 5s before transitioning high. the second option is called a software initiated power-up, which requires an initialize device fcs operation for a successful entry into reset mode. during an hcs initialize device operation, the load command register command is issued in the first cycle with chip initialize (68h) issued on a0Ca7, and a bank address issued on ba0, ba1. the
35 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash bank address is dont care, but the same bank ad- dress must be used for all three cycles. the second cycle is active, and the third cycle is write, during which c0h is issued on dq0-dq7. once the last com- mand is issued, the initialization sequence will com- mence. during an scs initialize device operation, eight commands on consecutive clock edges are required to input data to the array (nop, command inhibit, refresh, precharge, and burst terminate are permitted between cycles). after the first five setup cycles, the last three cycles are identical to a typical hcs, except the command for the first of the last three cycles is a write instead of an lcr. once the last command is issued, the initialization sequence will commence. the initialization sequence is completed either by allowing a time period of 100s to elapse or by checking for sr7 = 1. disable lcr sequence in some systems the sdram controller does not support the generation of the lcr command. these systems will likely find that the scs is more practical for performing flash operations. the disable lcr com- mand can be issued with either an hcs or scs opera- tion. once issued, the disable lcr bit will no longer allow hcs operations. note that unless disable lcr is issued, the device can function in either hcs or scs mode. reset/deep power-down mode to allow for maximum power conservation, the de- vice features a very low current, deep power-down mode. to enter this mode, rp# (reset/power-down) is taken to v ss 0.2v. to prevent an inadvertent reset, rp# must be held at v ss for at least 5s prior to the device entering the reset/deep power-down mode. after the device enters the reset/deep power-down mode, a transition from low to high on rp# results in a device power-up initialization sequence as outlined in the chip initial- ization section. when the device enters the deep power- down mode, all buffers excluding the rp# buffer are disabled and the current draw is a maximum of 50a at 3.3v v cc . the input to rp# must remain at v ss during deep power-down. entering the reset mode clears the status register. error handling after the ism status bit (sr7) has been set, the de- vice protect (sr3), write/protect block (sr4) and erase/ unprotect (sr5) status bits may be checked. if one or a combination of sr3, sr4, sr5 status bits has been set, an error has occurred. sr8 is set when an inadvertent power failure occurs during device initialization. the device should be reinitialized to ensure proper device operation. the ism cannot reset sr3, sr4, sr5, or sr8. to clear these bits, clear status register com- mand must be given. table 6 lists the combination of errors. program/erase cycle endurance syncflash memory is designed and fabricated to meet advanced code and data storage requirements. operation outside specification limits may reduce the number of program and erase cycles that can be performed on the device. each block is designed and processed for a minimum of 100,000-program/ erase-cycle endurance.
36 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash status bit # status register bit description sr15C reserved reserved for future use. sr9 sr8 v cc power sequence status (vps) vps is set if there has been a power disruption that may result in 1 = power-up incomplete error undefined device operation. a vps error is only cleared by 0 = power-up complete re-initializing the device. sr7 ism status (isms) the isms bit displays the active status of the state machine 1 = ready when performing program, block erase or chip initialize. 0 = busy the controlling logic polls this bit to determine when the erase and program status bits are valid. this bit can be monitored to determine the completion of power-up initialization after chip initialization sequence is issued. sr6 reserved reserved for future use. sr5 erase/unprotect block status (es) es is set to 1 after the maximum number of erase cycles is 1 = block erase or block executed by the ism without a successful verify. this bit is also set unprotect error to 1 if a block unprotect operation is unsuccessful. es is 0 = successful block erase or only cleared by a clear status register command or by a unprotect reset. sr4 program/protect block status (ws) ws is set to 1 after the maximum number of program cycles 1 = program or block protect error is executed by the ism without a successful verify. this bit is also 0 = successful block erase or set to 1 if a block or device protect operation is unprotect unsuccessful. ws is only cleared by a clear status register command or by a reset. sr3 device protect status (dps) dps is set to 1 if an invalid program, erase, protect 1 = device protected, invalid operation block, protect device or unprotect all blocks is met. attempted after one of these commands is issued, the condition of rp#, the 0 = device unprotected or rp# block protect bit and the device protect bit are compared to condition met determine if the desired operation is allowed. must be cleared by clear status register or by a reset. sr2 banka1 ism status (bisms) when sr0 = 0, the bank under ism control can be decoded from sr1 banka0 ism status sr1, sr2: [0,0] bank 0; [0,1] bank 1; [1,0] bank 2; [1,1] bank 3. sr1, sr2 is valid when sr7 = 0. when sr7 = 1, sr1, sr2 is reset to 0. sr0 device/bank ism status (dbs) dbs is set to 1 if the ism operation is a device-level operation. 1 = device-level ism operation a valid read to any bank can immediately follow the 0 = bank-level ism operation registration of an ism program operation. when dbs is set to 0, the ism operation is a bank-level operation. a read to the bank under ism control will output the contents of the row activated prior to the fcs. sr1 and sr2 can be decoded to determine which bank is under ism control. sr0 is used in conjuction with sr7, and is valid when sr7 = 0. when sr7 = 1, sr0 is reset to 0. note: 1. sr3Csr5 must be cleared with clear status register prior to initiating an ism write operation for the status bits to be valid. 2. x32: sr32-sr16 is a copy of sr15-sr0. table 4 status register bit definition 1 r vps isms r es ws dps bisms dbs 15C9 8 7 6 5 4 3 2C1 0
37 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash table 5 device configuration device configuration configuration address data condition notes manufacturer 000h xx2ch m anufacturer compatibility id read 1 compatibility id device id x32: 001h xxd4h device id read 1 x16: 001h xxd5h device id read 1 block protect bit x02h dq0 = 1 block protected 2, 3 x02h dq0 = 0 block unprotected device protect bit 003h dq0 = 1 block protect modification prevented 3 003h dq0 = 0 block protect modification enabled mode register 004h mode register definition data 4 hardware lcr disable 005h dq0 = 1 hardware lcr is disabled 3, 5 005h dq0 = 0 hardware lcr is enabled note: 1. dq8Cdq15 are dont care. for x32, dq31Cdq16 are a copy of dq15Cdq0. 2. address to read block protect bit is always the third location within each block. x32: x = 0, 2, 4, 6h; ba0, ba1 required. x16: x = 0, 4, 8, ch; ba0, ba1 required. 3. dq1Cdq7 are reserved, dq8Cdq15 are dont care. for x32, dq31Cdq16 are a copy of dq15Cdq0. 4. see figure 1 for more information. 5. factory preset is 0.
38 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash table 6 status register codes 1 status register code sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 state machine description 000h 000000000 busy C erase or program cycle for bank 0 001h 000000001 busy C block protect or unprotect cycle 002h 000000010 busy C erase or program cycle for bank 1 003h 000000011 busy C device protect cycle 004h 000000100 busy C erase or program cycle for bank 2 005h 000000101 busy C nvmode erase or program cycle 006h 000000110 busy C erase or program cycle for bank 3 007h 000000111 busy C initialization cycle 010h 000010000 busy C program cycle error for bank 0 011h 000010001 busy C block protect cycle error 012h 000010010 busy C program cycle error for bank 1 013h 000010011 busy C device protect cycle error 014h 000010100 busy C program cycle error for bank 2 015h 000010101 busy C nvmode program cycle error 016h 000010110 busy C program cycle error for bank 3 020h 000100000 busy C erase cycle error for bank 0 021h 000100001 busy C block unprotect cycle error 022h 000100010 busy C erase cycle error for bank 1 023h 000100011 busy C device unprotect cycle error 024h 000100100 busy C erase cycle error for bank 2 025h 000100101 busy C nvmode erase cycle error 026h 000100110 busy C erase cycle error for bank 3 080h 010000000 ready C no errors 090h 010010000 ready C program or protect cycle error 098h 010011000 ready C program/protect error and device/ block protection error 0a0h 010100000 ready C erase or unprotect cycle error 0a8h 010101000 ready C erase/unprotect error and device/ block protection error 0b0h 010110000 ready C command sequence error 0b8h 010111000 ready C command sequence error and device/block protection error 1xxh 1 xxxxxxxxv cc error (power-up without initialization error) note: 1. sr3Csr5 must be cleared using clear status register.
39 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash complete program status-check sequence self-timed program sequence 1 note: 1. sequence may be repeated for multiple programs. 2. fcs includes hcs and scs. 3. complete status check is not required. 4. the bank will be in array read mode. 5. sr3Csr5 must be cleared using clear status register. start fcs command sequence read status register polling sr7 = 1? complete status check program complete 4 3 no yes 2 start (program completed) sr4, sr5 = 1? yes command sequence error sr4 = 1? no yes no yes no 5 program successful sr3 = 1? invalid program error 5 program error 5
40 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash self-timed block erase sequence 1 complete block erase status-check sequence note: 1. sequence may be repeated to erase multiple blocks. 2. fcs includes hcs and scs. 3. rp# can be brought to v hh before the last command in the erase sequence is issued. 4. complete status check is not required. 5. the bank will be in the array read mode. 6. sr3Csr5 must be cleared using clear status register. fcs command sequence start read status register sr7 = 1 complete status check erase complete 5 4 yes no 2, 3 start (block erase completed) sr4, sr5 = 1? yes command sequence error sr5 = 1? no yes no yes no 6 block erase or unprotect error 6 erase or block unprotect successful sr3 = 1? invalid erase or unprotect error 6
41 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash block protect sequence 1 note: 1. sequence may be repeated for multiple block protects. 2. fcs includes hcs and scs. 3. rp# can be brought to v hh before the last command in the block protect sequence is issued. 4. complete status check is not required. 5. the bank will be in array read mode. 6. sr3Csr5 must be cleared using clear status register. start fcs command sequence 2, 3 complete status check device protect complete 4, 5 yes no read status register sr7 = 1 complete block protect status-check sequence start (block protect completed) sr4 = 1? block or device protect error 6 block protect successful sr3 = 1? invalid block/device protect error 6 sr4, sr5 = 1? yes command sequence error 6 no yes no yes no
42 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash device protect sequence 1 complete block status-check sequence note: 1. once the device protect bit is set, it can be reset. 2. fcs includes hcs and scs. 3. rp# can be brought to v hh before the last command in the device protect sequence is issued. 4. complete status check is not required. 5. a subsequent write command may be issued. start fcs command sequence 2, 3 complete status check device protect complete 4, 5 yes no read status register sr7 = 1 no fcs command sequence start read status register complete status check all blocks unprotect complete 4, 5 sr7 = 1 2 yes rp# = v hh device protected? unprotect blocks 1-14? no no yes yes
43 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash complete device protect status-check sequence start (device protect completed) sr4 = 1? block or device protect error 1 device protect successful sr3 = 1? invalid block/device protect error 1 sr4, sr5 = 1? yes command sequence error 1 no yes no yes no note: 1. sr3Csr5 must be cleared using clear status register.
44 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash absolute maximum ratings* voltage on rp# relative to v ss ...................... -1v to +9v voltage on v cc , v cc p, or v cc q supply, inputs, or i/os relative to v ss ........................ -1v to + 2.45v operating temperature, t a (ambient) ..................................... -40oc to +85oc storage temperature (plastic) ........... -55oc to +150oc power dissipation ........................................................ 1w short circuit output current ................................ 50ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up. (v cc , v cc p, and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.) dc electrical characteristics and operating conditions 1, 2 commercial temperature (-40oc t a +85oc); v cc = 3.0vC3.6v; v cc q = 1.65vC1.95v parameter/condition symbol min max unit v cc supply voltage v cc 3.0 3.6 v v cc q supply voltage v cc q 1.65 1.95 v hardware protection voltage v hh 7.0 8.5 v (rp# only) input high voltage: v ih 0.8 v cc qv cc q + 0.4 v logic 1; all inputs input low voltage: v il -0.3 0.3 v logic 0; all inputs input leakage current: any input 0v v in v cc i l -2 2 a (all other pins not under test = 0v) ouput leakage current: i oz -5 5 a dqs are disabled; 0v v out v cc q output high voltage: v oh v cc q - 0.2 C v i out = -100a output low voltage: v ol C 0.2 v i out = 100a
45 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash i cc specifications and conditions (notes: 1, 2, 3); extended temperature (-40oc t a +85oc); v cc = 3.0vC3.6v; v cc q = 1.65vC1.95v -8 -10 parameter/condition symbol max typ max typ units notes v cc operating current: i ccr 125 120 ma 4, 5, 6 read operation; burst mode all banks active; read; cas latency = 3 v cc operating current: i cca 100 95 ma 4 active operation all banks active v cc standby current: i ccs 1 10 10 ma active mode; cke = high; burst in progress v cc standby current: i ccs 2 22ma power-down mode; cke = low; no burst in progress v cc standby current: i ccs 3 200 200 a clock-quiet mode; clk = cke = low v cc deep power-down current: i ccdp 200 50 a rp# = v ss 0.2v or deep power-down command program current i ccw + i ppw 55 55 ma v cc p erase current i ppe 80 80 ma v cc p current: i pps 11a standby; power-down; deep power-down capacitance parameter symbol typ max units notes input capacitance: clk c i 1 2.5 4.0 p f 7 input capacitance: all other input-only pins c i 2 2.5 5.0 p f 7 input/output capacitance: dqs c io 4.0 6.5 p f 7 note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up. (v cc , v cc p, and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.) 3. i cc specifications are tested after the device is properly initialized. 4. i cc is dependent on output loading and cycle rates. specified values are obtained with the outputs open. 5. the i cc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 6. address transitions average one transition every 30ns. 7. this parameter is sampled. v cc = v cc q; f = 1 mhz, t a = +25oc. 8. typical conditions: +25 o c, burst length = 8, t rc = 140ns.
46 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash electrical characteristics and recommended ac operating conditions (notes: 1, 2, 3, 4, 5); extended temperature (-40oc t a +85oc); v cc = 3.0vC3.6v; v cc q = 1.65vC1.95v ac caracteristics -8 -10 parameter sym min max min max units notes access time from clk (pos. edge) cl = 3 t ac 7 7 ns cl = 2 t ac 8 8 ns cl = 1 t ac 19 22 ns address hold time t ah 1 1 ns address setup time t as 2 2 ns clk high level width t ch 3 3 ns clk low level width t cl 3 3 ns clock cycle time cl = 3 t ck 8 10 ns cl = 2 t ck 10 12 ns cl = 1 t ck 20 25 ns cke hold time t ckh 1 1 ns cke setup time t cks 2 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 2 2 ns data-in hold time t dh 1 1 ns data-in setup time t ds 2 2 ns data-out high-impedance time cl = 3 t hz 7 7 ns 6 cl = 2 t hz 8 8 ns 6 cl = 1 t hz 19 22 ns 6 data-out low-impedance time t lz 1 1 ns data-out hold time t oh 3 3 ns active command period t rc 60 60 ns active to read or write delay t rcd 24 30 ns active bank a to active bank b command t rrd 24 30 ns transition time t t 0.3 1.2 0.3 1.2 ns 7 note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100s is required after power-up. (v cc , v cc p, and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.) 3. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. outputs measured at 0.8v with equivalent load: 5. ac timing and i cc tests have v il = 0v and v ih = 1.6v, with timing referenced to 0.8v crossover point. 6. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 7. ac characteristics assume t t = 1ns. q 30pf x32 q 50pf x16
47 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. an initial pause of 100s is required after power-up. (v cc , v cc p, and v cc q must be powered up simultaneously. v ss and v ss q must be at same potential.) 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 0.8v with equivalent load: q 50pf x16 q 30pf x32 6. ac timing and i cc tests have v il = 0v and v ih = 1.6v, with timing referenced to 0.8v crossover point. 7. required clocks specified by jedec functionality and not dependent on any timing parameter. 8. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. ac functional characteristics (notes: 1-6); extended temperature (-40oc t a +85oc); v cc = 3.0vC3.6v; v cc q = 1.65vC1.95v parameter symbol -8 -10 units notes read/write to read/load command register command t ccd 1 1 t ck 7 cke to clock disable or power-down entry mode t cked 1 1 t ck 8 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 8 dqm to input data delay t dqd 0 0 t ck 7 dqm to data mask during writes t dqm 0 0 t ck 7 dqm to data high-impedance during reads t dqz 2 2 t ck 7 write command to input data delay t dwd 0 0 t ck 7 data-in to active command t dal 5 5 t ck data-in to active terminate command t dpl 2 2 t ck load mode register command to active command t mrd 2 2 t ck 7 data-out to high-z from active terminate command cl = 3 t roh 3 3 t ck 7 cl = 2 t roh 2 2 t ck 7 cl = 1 t roh 1 1 t ck
48 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. advance 64mb: x16, x32 syncflash memory flash initialize and load mode register (rp# control) t ch t cl cke ta clk tm tn + 2 tn + 3 command dq address opcode t mrd load mode register 3, 4, 5 t cms power-up: 2 v cc , v cc p, v cc q, clk stable t = 100s t ah t as row load mode register nop active high-z dqm v cc , v cc p, v cc q dont care undefined tn tn + 1 t ck t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) rp# 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) timing parameters -8 -10 symbol* min max min max units t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns *cas latency indicated in parentheses. -8 -10 symbol* min max min max units note: 1. rp# = v cc or v hh 2. v cc = 3.3v, v cc p = 3.3v, v cc q = 1.8v 3. the nvmode register contents are automatically loaded into the mode register upon power-up initialization, load mode register cycle is required to enter new mode register values. 4. jedec and pc100 specify three clocks. 5. if cs is high at clock time, all commands applied are nop, with cke a dont care. t ck(1) C C ns t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t mrd 2 2 t ck
49 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance initialize and load mode register (fcs control) t ch t cl cke ta clk tm tn + 2 tn + 3 command dq address opcode t mrd load mode register 3, 4, 5 t cms power-up: 2 v cc , v cc p, v cc q, clk stable t = 100s t ah t as row load mode register nop active high-z dqm v cc , v cc p, v cc q dont care undefined tn tn + 1 t ck t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) rp# 1 ( ) ( ) ( ) ( ) ( ) ( ) write 6 c0h ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) timing parameters -8 -10 symbol* min max min max units t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns *cas latency indicated in parentheses. -8 -10 symbol* min max min max units note: 1. rp# = v cc or v hh 2. v cc = 3.3v, v cc p = 3.3v, v cc q = 1.8v 3. the nvmode register contents are automatically loaded into the mode register upon power-up initialization, load mode register cycle is required to enter new mode register values. 4. jedec and pc100 specify three clocks. 5. if cs is high at clock time, all commands applied are nop, with cke a dont care. t ck(1) C C ns t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t mrd 2 2 t ck
50 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance clock suspend mode 1 t ch t cl t ck t ac t lz dqm clk dq ba t oh d out m t ah t as t ah t as t ac t hz d out m+1 command t cmh t cms t cmh t cms nop nop nop nop nop read dont care undefined cke t cks t ckh bank column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 x32: a0Ca10 x16: a0Ca11 note: 1. for this example, the burst length = 2, cas latency = 3. 2. a0Ca7 timing parameters -8 -10 symbol* min max min max units t ac(3) 7 7 ns t ac(2) 8 8 ns t ac(1) C C ns t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns t ck(1) C C ns t ckh 1 1 ns *cas latency indicated in parentheses. -8 -10 symbol* min max min max units t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t dh 1 1 ns t ds 2 2 ns t hz(3) 7 7 ns t hz(2) 8 8 ns t hz(1) C C ns t lz 1 1 ns t oh 3 3 ns
51 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance read 1 note: 1. for this example, the burst length = 4, cas latency = 2. 2. a0Ca7. t ch t cl t ck t ac t lz t rcd cas latency t rc dqm cke clk dq ba t oh d out m t ah t as t ah t as column m 2 row bank bank row bank dont care undefined t hz t oh d out m+3 t ac t oh t ac t oh t ac d out m+2 d out m+1 command t cmh t cms t cmh t cms nop nop nop active nop read nop active nop t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 x32: a0Ca10 x16: a0Ca11 timing parameters -8 -10 symbol* min max min max units t ac(3) 7 7 ns t ac(2) 8 8 ns t ac(1) C C ns t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns t ck(1) C C ns *cas latency indicated in parentheses. -8 -10 symbol* min max min max units t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t lz 1 1 ns t oh 3 3 ns t rc 60 60 n s t r c d 24 30 n s t r r d 24 30 n s
52 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance read C alternating bank read accesses 1 t ch t cl t ck t ac t lz dqm clk dq ba t oh d out m t ah t as t ah t as column m 2 row row dont care undefined t oh d out m+3 t ac t oh t ac t oh t ac d out m+2 d out m+1 command t cmh t cms t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read column b 2 active row bank 0 bank 0 bank 1 bank 1 bank 0 cke t ckh t cks t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 1 cas latency - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 x32: a0Ca10 x16: a0Ca11 note: 1. for this example, cas latency = 2. timing parameters -8 -10 symbol* min max min max units t ac(3) 7 7 ns t ac(2) 8 8 ns t ac(1) C C ns t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns t ck(1) C C ns *cas latency indicated in parentheses. -8 -10 symbol* min max min max units t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t lz 1 1 ns t oh 3 3 ns t rc 60 60 n s t r c d 24 30 n s t r r d 24 30 n s
53 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance read C full-page burst 1 note: 1. for this example, the cas latency = 2. 2. a0Ca7. timing parameters -8 -10 symbol* min max min max units t ac(3) 7 7 ns t ac(2) 8 8 ns t ac(1) C C ns t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns t ck(1) C C ns *cas latency indicated in parentheses. -8 -10 symbol* min max min max units t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t hz(3) 7 7 ns t hz(2) 8 8 ns t hz(1) C C ns t lz 1 1 ns t oh 3 3 ns t r c d 24 30 n s t ch t cl t ck t ac t lz t rcd cas latency dqm cke clk dq ba oh d out m t ah t as t ac t oh d out m+1 row t hz t ac t oh d out m+1 t ac t oh d out m+2 t ac t oh d out m-1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed. 256 (x16), 128 (x32) locations within the same row. dont care undefined command t cmh t cms t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop column m 2 t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 t3 t4 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 x32: a0Ca10 x16: a0Ca11
54 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance read C dqm operation 1 note: 1. for this example, the burst length = 4, cas latency = 2. 2. a0Ca7. t ch t cl t ck t rcd cas latency dqm cke clk dq ba bank row bank dont care undefined t ac lz d out m t oh d out m+3 d out m+2 t t hz lz t command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t ah t as t cms t cmh t cms t cmh column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 x32: a0Ca10 x16: a0Ca11 *cas latency indicated in parentheses. timing parameters -8 -10 symbol* min max min max units t ac(3) 7 7 ns t ac(2) 8 8 ns t ac(1) C C ns t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns t ck(1) C C ns -8 -10 symbol* min max min max units t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t hz(3) 7 7 ns t hz(2) 8 8 ns t hz(1) C C ns t lz 1 1 ns t oh 3 3 ns t r c d 24 30 n s
55 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance program/erase 1 (bank a followed by read to bank a ) t ch t cl t ck dqm cke clk ba dq row bank a d in 4 m t dh t ds command t cmh t cms read nop active nop write lcr nop bank a bank a t ah t as t ckh t cks nop nop nop column 3 m t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 comcode 2 dont care undefined t rcd high-z dout n bank a column n dh t t ds dout n+1 t cmh t cms x32: a0Ca10 x16: a0Ca11 note: 1. active/read or read will output the contents of the row activated prior to the lcr/active/write command sequence. this exampl e illustrates the timing for activating a new row in bank a . for this example, read burst length = 2, cas latency = 2. 2. comcode = 40h for program, 20h for erase (see truth table 2). 3. lcr/active cycles must be initiated prior to read according to truth table 2 for a status register read command sequence. 4. column address is dont care for erase operation. 5. d in = d0h (erase confirm) for erase operation. *cas latency indicated in parentheses. timing parameters -8 -10 symbol* min max min max units t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns -8 -10 symbol* min max min max units t ck(1) C C ns t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t mrd 2 2 t ck
56 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance t ch t cl t ck dqm cke clk x32: a0-a10 x16: a0-a11 ba dq t cmh t cms bank b row bank a d in 4 m t dh t ds t ds command t cmh t cms read nop active nop write lcr nop bank a column n bank a t ah t as t dh t ckh t cks nop nop nop column 3 m t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 comcode 2 dont care undefined t rcd d out n d out n + 1 high-z program/erase 1 (bank a followed by read to bank b ) note: 1. for this example, read burst length = 2, cas = 3. 2. comcode = 40h for write, 20h for erase (see truth table 2). 3. column address is dont care for erase operation. 4. d in = d0h (erase confirm) for erase operation. *cas latency indicated in parentheses. timing parameters -8 -10 symbol* min max min max units t ah 1 1 ns t as 2 2 ns t ch 3 3 ns t cl 3 3 ns t ck(3) 8 10 ns t ck(2) 10 12 ns -8 -10 symbol* min max min max units t ck(1) C C ns t ckh 1 1 ns t cks 2 2 ns t cmh 1 1 ns t cms 2 2 ns t mrd 2 2 t ck
57 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance 90-ball fbga pin a1 id substrate: plastic laminate encapsulation material: epoxy novolac solder ball material: eutectic 63% sn, 37% pb. or 62% sn, 36% pb, 2% ag solder ball pad: ? .33mm seating plane .850 .075 ball a9 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.40mm .10 c c 13.00 .10 .80 typ 11.20 1.20 max 5.60 .05 6.50 .05 pin a1 id ball a1 .80 typ 5.50 .05 3.20 .05 11.00 .10 6.40 0.45 90x ? c l c l note: 1. all dimensions in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron, the m logo, and syncflash are registered trademarks, and the micron logo is a trademark of micron technology, inc. data sheet designation advance: this data sheet contains initial descriptions of products still under development.
58 64mb: x16, x32 syncflash micron technology, inc., reserves the right to change products or specifications without notice. mt28s4m16b1ll.p65 C rev. 1, pub. 5/02 ?2002, micron technology, inc. 64mb: x16, x32 syncflash memory advance revision history original document, rev. 1, advance ............................................................................................. ..................... 4/02

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